aal5 sar with atm-to-mpls interworking product overview portmakeriii firmware provides proven, reliable, and fully supported binary applications for the TSP3 family of devices. the portmakeriii aal5 sar with atm-to-mpls interworking application is one of a suite of off-the-shelf applications for the TSP3 hardware platform. it provides up to oc-48 throughput saring, fine-grained traffic management, atm- to-mpls interworking support, and a rich set of value-added features. the firmware is also available with a source code license to allow product differentiation and multi-service operation with other portmakeriii or custom applications. aal5 segmentation and reassembly (sar) the portmakeriii aal5 application complies with the itu i.363.5 standard and also conforms to the atm forum pics proforma for aal type 5 tests. the firmware runs across the entire TSP3 family, providing a maximum of 256k connections and up to 2.5 gbps rates. atm cell traffic uses either the utopia or pos interfaces for streaming mode operation, while packet traffic can use the pos interface for streaming mode opera- tion, or the pci bus for shared memory operation. host-based management of the sar is accomplished via the pci bus using commands, acknowledgements, indications, and alarms. traffic shaping traffic shaping is provided at the output of both the segmentation and reassembly functions. in the segmentation direction, each connection has two generic cell rate algo- rithms (gcras) that support cbr, vbr, ubr, and ubr+ as defined in the atm forum traffic management 4.1 specification. the host selects the shaping parameters and priority on a per vc basis at open channel time. a four-level, strict priority scoreboard-based mechanism is used to schedule cells for transmission, allowing quality of service (qos) level guarantees. shaping rates are available from 64 kbps to 100 percent of line rate, within one percent accuracy. buffer management up to 256 mbytes of local sdram are supported for buffering traffic. two pools of buffers are supported: internal buffers and host buffers. internal buffers occupy local sdram and are 128-bytes in length. internal buffers are allocated to one of 16 buffer classes during initialization. host buffers are configurable in size and can be placed either in local sdram or in host memory on the pci bus. host buffers are optionally used for packet output from the reassembler, when the shared memory mode of operation is used. congestion control segmenter packets are stored in per-vc queues. queue admission is controlled by one of three methods, selected at open channel time: weighted random early discard (wred), per-vc flow control, and per-vc epd. > runs across entire family of TSP3 devices > itu i.363.5 compliant aal5 sar > atm forum tm4.1 traffic shaping > traffic shaping rates config- urable from 64 kbps to 100 percent of li ne-rate, within one percent accuracy > independent shaping and policing profiles for up to 256k connections > supports up to 64 phys at 64 independent rates > choice of segmenter queue admission policies (wred, per vc epd, and per vc flow control) > vp tunnels with wrr and vc tunnels with cbwfq > atm-to-mpls interworking support based on ietf-pwe3- atm-encap > ingress policing > auto-vc discovery > integrated oam cell processing > encapsulation / de-encapsulation > per-phy and per- connection statistics > pci based evm, portbuilder??iii host driver, and consulting services to accelerate time-to-market > > key features portmaker?iii aal5 firmware TSP3 traffic stream processors
www.mindspeed.com/salesoffices general information: (949) 579-3000 headquarters C newport beach 4000 macarthur blvd., east tower newport beach, ca 92660-3007 mxapm3a5-brf-001-a m03-0778 ? 2003 mindspeed technologies, inc. all rights reserved. mindspeed and the mindspeed logo are trademarks of mindspeed technologies. all other trademarks are the property of their respective owners. although mindspeed technologies strives for accuracy in all its publications, this material may contain errors or omissions and is subject to change without notice. this material is provided as is and without any express or implied warranties, including merchantability, fitness for a particular purpose and non-infringement. mindspeed technologies shall not be liable for any special, indirect, incidental or consequential damages as a result of its use. functions ? itu i.363.5 aal5 sar ? up to oc-48c throughput ? a maximum of 256k connections ? supports up to 64 phys at 64 different rates ? traffic shaping C dual gcra per connection ? supports the following traffic shaping conformance definitions: - cbr.1, vbr.1 (rt, nrt), ubr.1, ubr.2, ubr+ ? vp tunnels with wrr access ? vc tunnels with cbwfq access ? congestion control - wred, per vc flow control, per vc epd ? atm-to-mpls interworking based on ietf-pwe3-atm-encap ? reassembly time-out ? encapsulation / de-encapsulation ? support for raw cells (aal0) ? integrated oam cell processing ? ingress policing ? auto-vc discovery ? host control via pci bus ? per-connection and per-port statistics see the TSP3 traffic stream processor data sheet for a description of the hardware interfaces, memory requirements, and device characteristics. product features the wred algorithm discards packets in a manner that optimizes the overall network performance of tcp/ip connections. up to 128 sets of wred parameters are supported, selected on a per packet basis. the per-vc flow control option sends indications to the host when a config- urable high and low threshold are crossed (with hysteresis). per-vc epd is similar to flow control except that packets are dropped when the high threshold is exceeded, and no indications are sent. both the segmenter and reassembler provide per-buffer-class epd when a configurable threshold is exceeded, and partial packet discard (ppd) when the buffer class is exhausted. vp tunnels with weighted round robin a segmenter vp tunnel consists of a group of vcs, each of which gains access to the tunnel using a weighted round robin scheme. this allows proportional bandwidth sharing among the vcs. the tunnel itself is then shaped in the same manner as ordinary vcs. up to 32k vp tunnels are supported. vc tunnels with class based weighted fair queuing a segmenter vc tunnel provides up to eight class of service (cos) queues, allowing packets from each cos queue to be multiplexed onto a single channel. the cos queues are serviced using a class- based weighted fair queuing (cbwfq) algorithm with a low latency- mode. fairness is measured on a per-cell basis, however, full packets are transmitted at a time. the tunnel itself is then shaped in the same manner as ordinary vcs. up to 32k vc tunnels, each with 8 cos queues, are supported. atm-to-mpls interworking portmakeriii supports ietf-pwe3-atm-encap (draft-martini) and can be run concurrently with aal5 segmentation-and-reassembly channels, selectable on a per channel basis. this cell-bundling function provides the basis of interworking atm-to- mpls in order to provide efficient transport of atm over an ip/mpls network core. for cell bundling, atm cells are received, header transla- tion is performed, and a configurable number of cells are bundled into an mpls packet. for bundling, mpls packets are received on egress, atm cells are unbundled individually from the packet, and traffic management criteria are then applied for the channel. timers are used to control latency during bundle creation. encapsulation / de-encapsulation the segmenter offers optional 8- or 10-byte encapsulation, supporting routed ipv4 and bridged ethernet pdus as defined in rfc 2684/1483. the reassembler offers optional stripping of up to 31 bytes. all encap- sulation and de-encapsulation parameters are determined on a per channel basis. other formats can be readily supported. applications the portmakeriii firmware is intended for use in enterprise, aggregation, edge and core routers, multi-service edge switches, optical edge equipment, dslams, and fixed and mobile wireless equipment. a typical oc-48 application using two m27483 devices running portmakeriii is shown below. figure 1: bi-directional oc-48 system line host processor input system port 0 line egress port 0 line egress port 1 line egress port 63 line egress port 63 system ingress port 0 system ingress port 3 line egress port 0 line egress port 1 urx0 utx0 utx0 urx0 pci pci input/output system port m27483 m27483 aal5 segmentation aal5 reassembly input/output system port (phy) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . system egress
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